• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    An object of the present invention is to provide a semiconductor integrated circuit device capable of reducing the circuit scale by simplifying the configuration related to the test function while maintaining the advantages such as real-time testing. When the DRAM memory array 2a to be tested and the operation mode are set to the test mode, the ALPG 4 which writes and reads test data to the DRAM memory array 2a and the data recording by the ALPG 4 CPU 6, which reads the data held in the memory cell at the time of reading, analyzes the position determination of the defective portion in the DRAM memory array 2a, and the redundant configuration portion in which the defective portion is to be replaced; A CPU SRAM 7 for storing the execution code, the failure determination result, and the analysis result of the above operation in the test mode.
    公开号:KR20030085466A
    申请号:KR10-2003-0001948
    申请日:2003-01-13
    公开日:2003-11-05
    发明作者:구로다사치에
    申请人:미쓰비시덴키 가부시키가이샤；
    IPC主号:
    专利说明:

    Semiconductor integrated circuit device {REPAIR ANALYZER OF DRAM IN SEMICONDUCTOR INTEGRATED CIRCUIT USING BUILT-IN CPU}
    [23] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuit devices such as system LSIs, and more particularly, to a device for analyzing DRAMs in semiconductor integrated circuit devices by a central processing unit (CPU) embedded in a semiconductor integrated circuit device.
    [24] FIG. 9 is a diagram showing a schematic configuration of a conventional semiconductor integrated circuit device having a built-in self test (BIST) circuit of a DRAM, and FIG. 10 is a diagram illustrating a defect repair analysis of a DRAM by the BIST circuit of FIG. It is a figure which shows a structure. In the figure, reference numeral 100 denotes a semiconductor integrated circuit device including a DRAM core 101, a BIST circuit 104, a logic circuit section 107, and the like in one chip. Reference numeral 101 denotes a DRAM core, a DRAM memory array in which memory cells are arranged on grid lines of word lines and bit lines, column row decoders for selecting memory cells on the DRAM memory array, word drivers, and bit line selection circuits. And a sense amplifier for amplifying and outputting the read data from the memory cell. The DRAM core 101 also includes a spare row and spare row decoder for repairing defective memory cells existing in the DRAM memory array, and a spare column and a spare column decoder.
    [25] 102 is a memory for ALPG, which stores a test vector and an access pattern program for executing a test on a DRAM memory array using the same. Here, the test vector is a program describing the input vector and the expected output vector (expected value) in a test program language. In addition, an access pattern program (main program) is a program which describes the operation control procedure of each structure part which concerns on the test function at the time of a test. When the ALPG 103 executes this access pattern program, a test vector is used as a test pattern composed of an input signal sequence conforming to the test specification and the expected response output signal sequence (expected value data). In addition, a test program is composed of these test patterns and access pattern programs.
    [26] Reference numeral 103 is an ALPG (ALgorithmic Pattern Generator) that generates an address and data for a DRAM test by using an arithmetic circuit, and executes a test program to generate test pattern data having a predetermined bit pattern to generate a test pattern data in the DRAM core 101. Write to the memory cell is executed. A 104 is a BIST circuit, and is composed of an ALPG memory 102, an ALPG 103, a defect relief analyzer 105, and a failure analysis memory 106. 105 is a failure relief analyzer that determines whether or not the test pattern data written to the DRAM memory cell array by the ALPG 103 is read normally to generate compressed information RD of information about the defective memory cell. The failure relief analyzer 105 is composed of a comparator for logically comparing the output data and the expected value of the DRAM, a test output compressor for compressing the failure information, and the like. In this case, hardware according to a test specification is used as the test output compressor, and generally includes a counter or a linear feedback shift register (LFSR).
    [27] Reference numeral 106 denotes a failure analysis memory for storing compressed information about a defective memory cell obtained as a result of a test of the entire memory area of the DRAM, and an SRAM capable of writing and reading data at any time is used. Reference numeral 107 denotes a logic circuit that executes logic arithmetic processing of the semiconductor integrated circuit device 100, and includes a control register that stores the CPU 108, the SRAM 109, the operation mode, and the instruction code from the CPU 108. Reference numeral 108 denotes a CPU, and 109 denotes a CPU SRAM, which temporarily stores execution code of a normal user program by the CPU 108. Reference numeral 110 denotes a write circuit, which reads an access pattern program from an external test apparatus such as an LSI tester and stores it in the memory 102 for ALPG. Reference numeral 111 denotes an LT-fuse which is laser trimmed upon defective relief.
    [28] Next, the operation will be described.
    [29] First, the ALPG memory 102 that stores a plurality of test vectors corresponding to various test modes is stored, via the write circuit 110, from an external test apparatus such as an LSI tester according to a test specification. Subsequently, when a logic value indicating test start is written to a predetermined bit of a control register (not shown) in the BIST circuit 104, the ALPG 103 reads the test program from the memory for ALPG 102, and the access timing corresponding thereto. And generate test pattern data to initiate access to the DRAM memory array. Here, for example, it is assumed that the ALPG 103 repeats the write / read access to one memory cell of the DRAM memory cell array a plurality of times.
    [30] Specifically, in the write access, the ALPG 103 generates an address signal which specifies the address of the memory cell to be data written in accordance with the access timing described in the access pattern program, so that the column in the DRAM core 101. Send to the row decoder. The column row decoder decodes the address signal from the ALPG 103 and converts it into address information on the DRAM memory array. This address information is sent to a word driver and a bit line selection circuit to select a memory cell for data writing. For each memory cell selected in this way, the ALPG 103 writes test pattern data. On the other hand, in the read access, the target memory cell is selected in the same manner as described above, and the ALPG 103 reads out data.
    [31] Subsequently, when a plurality of accesses to one memory cell are completed, the defective relief analyzer 105 detects the stored data of the memory cell specified by the address signal from the ALPG 103 and outputs from the corresponding memory cell. Enter as data. At this time, the defective relief analyzer 105 logically compares the expected value data input from the ALPG 103 with the corresponding output data.
    [32] Here, if it is determined that there is any defect in the corresponding memory cell because the two do not match, the defect relief analyzer 105 effectively rescues the defective memory cell in the DRAM memory array based on the information about the defective memory cell. A set of replacement addresses (redundancy relief) for determining the row or column to be determined is obtained. Here, the information about the bad memory cell (hereinafter referred to as bad information) is address information for specifying an address position on the DRAM memory array of the bad memory cell, an index indicating the bad state, and the like. As an index indicating a bad state, for example, bit data indicating whether all of the plurality of accesses match at the H level, the L level, or are mixed (high impedance) can be considered.
    [33] Based on the redundant redundancy solution obtained for the defective memory cell, the defective relief analyzer 105 generates compressed information obtained by compressing the defective information in relief units. For example, if the DRAM memory array has a configuration for performing redundancy relief in units of bit lines including defective memory cells, data is replaced by replacing one piece of defective information on a plurality of memory cells having different addresses on the same line with one data. Is compressed. The compressed information thus obtained is stored in the failure analysis memory 106 as a series of operations in the read access.
    [34] Thereafter, the failure relief analyzer 105 executes a test on all memory cells of the DRAM memory array under test, and gradually stores the found failure information in the failure analysis memory 106 as compressed information.
    [35] When the test for all the memory cells of the DRAM memory array under test is completed, the logic value indicating the end of the test is written to the predetermined bit of the control register (not shown) in the BIST circuit 104, and the test process ends. Subsequently, the defect relief analyzer 105 analyzes the compressed information accumulated in the memory for failure analysis 106 in the CPU 108 in the logic circuit section 107, and selects a portion of the LT-fuse 111 to be laser trimmed. Get the rescue code you specify. The relief code is read by an external test apparatus such as an LSI tester, and actual defect relief is performed.
    [36] Since the conventional semiconductor integrated circuit device is configured as described above, there is a problem that the circuit scale inevitably increases due to the existence of the defect analysis memory 106 and the defect relief analyzer 105 used only for testing.
    [37] For example, the failure relief analyzer 105 stores, in the address corresponding to the internal address of the DRAM memory array, the failure information of the memory cell corresponding to the address one by one. This corresponds to reproducing the internal failure information of the DRAM memory array on the failure analysis memory 106. For this reason, the failure analysis memory 106 requires a storage capacity corresponding to the address to be acquired for the DRAM memory array under test, regardless of the number of defect information. In other words, there is a built-in memory of almost the same storage capacity in one semiconductor integrated circuit device.
    [38] SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and by simplifying the analysis of the defects in the semiconductor memory device by software processing by the CPU, the configuration related to the test function can be simplified while maintaining the advantages such as real-time testing. An object of the present invention is to obtain a semiconductor integrated circuit device which can be scaled down.
    [1] 1 is a diagram showing a schematic configuration of a semiconductor integrated circuit device according to Embodiment 1 of the present invention;
    [2] FIG. 2 is a diagram showing a configuration for performing defect relief analysis of DRAM of the semiconductor integrated circuit device in FIG. 1; FIG.
    [3] 3 is a flowchart illustrating an operation of the semiconductor integrated circuit device of FIG. 1;
    [4] 4 is a diagram showing a schematic configuration of a semiconductor integrated circuit device according to Embodiment 2 of the present invention;
    [5] FIG. 5 is a diagram showing a configuration for performing defect relief analysis of a DRAM of the semiconductor integrated circuit device in FIG. 4; FIG.
    [6] 6 is a flowchart illustrating an operation of the semiconductor integrated circuit device of FIG. 4;
    [7] 7 is a diagram showing a schematic configuration of a semiconductor integrated circuit device according to Embodiment 3 of the present invention;
    [8] FIG. 8 is a diagram illustrating a configuration for performing defect relief analysis of DRAM of the semiconductor integrated circuit device in FIG. 7; FIG.
    [9] 9 is a diagram showing a schematic configuration of a conventional semiconductor integrated circuit device;
    [10] FIG. 10 is a diagram showing a configuration for performing defect relief analysis of a DRAM by the BIST circuit in FIG. 9; FIG.
    [11] Explanation of symbols for the main parts of the drawings
    [12] DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit device 2 DRAM core (semiconductor memory device)
    [13] 2a: DRAM memory array (semiconductor memory)
    [14] 3: memory for ALPG 4: ALPG (test access unit)
    [15] 5 logic circuit 6 CPU (central processing unit)
    [16] 7: SRAM (Memory) 7a: Program Memory Area
    [17] 7b: ES memory area 7c: RC memory area
    [18] 8: recording circuit 9: LT-fuse
    [19] 10: TIC11: control register
    [20] 12: buffer memory 13: bad judgment flag
    [21] 14: comparison circuit (comparison circuit section) 15: selector
    [22] 16: relief line flag
    [39] The semiconductor integrated circuit device according to the present invention comprises a semiconductor memory device consisting of a plurality of memory cells and having a redundancy component configured to replace defective parts and a memory cell in the semiconductor memory device when the operation mode is set to the test mode. The test access unit for writing and reading the test data and the data held in the memory cell at the time of data writing and reading by the test access unit are read again to determine the position of the defective part in the semiconductor storage device and determine the defective part. And a storage unit for storing the execution code, the failure determination result, and the analysis result of the operation in the test mode of the central processing unit.
    [40] A semiconductor integrated circuit device according to the present invention includes a comparison circuit section for performing comparison between data held in a memory cell and its expected value during data writing and reading by a test access section, and a memory block corresponding to a replacement unit of a redundant configuration section. A defect determination flag is set for each defect, and the central processing unit reads data again only to the memory cells in the memory block in which the comparison result by the comparing circuit unit is not matched and the defect is determined to be defective. The determination of the position of the defective part in the memory block and the redundant configuration to replace the defective part are performed.
    [41] The semiconductor integrated circuit device according to the present invention comprises a bit line and a word line arranged in a matrix shape by a semiconductor memory device and a plurality of memory cells arranged on these lattice points, and writes data to the memory cell by the test access unit. At the time of reading, it has a relief line flag in which the information which specifies the bit line and / or word line which existed the predetermined number or more of defective parts is set, and a central processing unit sets the bit line and / or word line set to the relief line flag. First, analysis of the redundant components to be replaced is performed so as not to determine the position of the defective part with respect to the bit line and / or word line.
    [42] A test method for a semiconductor integrated circuit device according to the present invention comprises a semiconductor memory device consisting of a plurality of memory cells and having a redundant configuration to replace defective parts and a memory in the semiconductor memory device when the operation mode is set to the test mode. In a test method of a semiconductor integrated circuit device having a test access section for writing and reading test data to a cell, the test code for the operation in the test mode is stored in a storage unit that stores the execution code of the central processing unit. In accordance with the execution code in the test mode, the central processing unit reads the data held in the memory cell again during data writing and reading by the test access unit, and performs a defective determination in determining the position of the defective portion in the semiconductor storage device. And the defective unit obtained by the central processing unit in the failure determination step. And a relief analysis step of analyzing the redundant component to replace the minute, and storing the analysis result and the position determination result of the defective part in the storage unit.
    [43] The above and other objects, features, aspects, advantages, and the like of the present invention will become more apparent from the following detailed embodiments described with reference to the accompanying drawings.
    [44] Hereinafter, an embodiment of the present invention will be described.
    [45] (Example 1)
    [46] 1 is a diagram showing a schematic configuration of a semiconductor integrated circuit device according to Embodiment 1 of the present invention. In the figure, reference numeral 1 denotes a semiconductor integrated circuit device according to Embodiment 1, which includes a DRAM core 2, an ALPG memory 3, an ALPG 4, a logic circuit section 5, and the like in one chip. It is composed. (2) shows a DRAM core (semiconductor storage device), which is a DRAM memory array formed by arranging memory cells on a lattice point between a word line and a bit line, a column-row decoder for selecting memory cells on the DRAM memory array, a word driver and a bit. And a sense amplifier for amplifying and outputting read data from the memory cell. In addition, the DRAM core 2 is supposed to include a spare row and a spare row decoder, and a spare column and a spare column decoder for repairing bad memory cells existing in the DRAM memory array.
    [47] (3) is an ALPG memory which is a storage area of the execution code (the so-called machine code) of the ALPG 4, which stores a test vector and an access pattern program for executing a test on a DRAM memory array using this as appropriate. Here, the test vector is a program describing the input vector and the expected output vector (expected value) in a test program language. In addition, an access pattern program (main program) is a program which describes the operation control procedure of each structure part which concerns on the test function at the time of a test. When the ALPG 4 executes this access pattern program, a test vector is used as a test pattern composed of an input signal sequence conforming to the test specification and the expected response output signal sequence (expected value data). In addition, a test program is composed of these test patterns and access pattern programs.
    [48] Reference numeral 4 denotes an ALPG (test access unit) which generates an address and data for a DRAM test by using a calculation circuit. The test program is executed by generating a test pattern data having a predetermined bit pattern by executing a test program. Write to the memory cell is executed. Reference numeral 5 denotes a logic circuit that executes logic arithmetic processing of the semiconductor integrated circuit device 1, and includes a control register that stores a CPU 6, an SRAM 7, an operation mode, and an instruction code from the CPU 6. And a selector for obtaining address information at the time of compression. Numeral 6 denotes a CPU (central processing unit) that executes a user program stored in a ROM (not shown) in the normal mode, and analyzes the defective defect of the DRAM when the test mode is set.
    [49] (7) is a CPU SRAM (memory unit), which temporarily stores the execution code of a normal user program by the CPU 6, and further includes a test program, a program for remedy analysis, and defective information obtained by this defect remedy analysis. Stores compressed information or relief codes. Reference numeral 8 denotes a write circuit which reads a test program from an external test apparatus such as an LSI tester and stores it in the ALPG memory 3 and the SRAM 7. (9) is the LT-fuse which is laser trimmed at the time of defective remedy.
    [50] FIG. 2 is a diagram showing a configuration for performing defect relief analysis of the DRAM of the semiconductor integrated circuit device in FIG. 1. In the figure, reference numeral 2a denotes a DRAM memory array (semiconductor storage device) constituting the DRAM core 2, in which data writing and reading in the test mode is performed via the TIC 10. In FIG. (7a) is a program memory area provided in the memory area of the SRAM 7, and temporarily stores the execution code of the program by the CPU 6, and also stores the test program and the relief analysis program input from the recording circuit 8; Save it. 7b is an ES memory area (error storage memory area) provided in the memory area of the SRAM 7 and stores defective information obtained by the DRAM test by the CPU 6. 7c is an RC memory area (relief code memory area) provided in the memory area of the SRAM 7, and stores the relief code obtained by the CPU 6 based on the defect information.
    [51] Reference numeral 10 denotes a TIC (Test-Interface-Circuit), which relays data input / output between the logic circuit section 5 and the DRAM memory array 2a under test. Reference numeral 11 denotes a control register that stores the operation code of the semiconductor integrated circuit device 1 and the instruction code from the CPU 6. Reference numeral 12 denotes a buffer memory that temporarily stores data obtained by the execution of a program by the CPU 6. In addition, the same code | symbol is attached | subjected to the same component as FIG. 1, and the overlapping description is abbreviate | omitted.
    [52] Next, the operation will be described.
    [53] FIG. 3 is a flowchart showing the operation by the semiconductor integrated circuit device shown in FIG. 1, and the defect relief analysis operation of the DRAM will be described according to this drawing.
    [54] First, the recording circuit 8 inputs information necessary for a test such as a test program according to a test specification from an external test device such as an LSI tester. Thereafter, the write circuit 8 sets the input test program in the ALPG memory 3 and the program memory area 7a in the SRAM 7 as execution codes of the ALPG 4 and the CPU 6, respectively. In addition, this setting operation is performed in accordance with the data setting speed of the external test apparatus.
    [55] Next, when the CPU 6 receives a test start request from the outside, the control register 11 stores a logic value specifying an access pattern program and a test vector of the test specification according to the request, and a logic value indicating the start of the test. ) Is set to a predetermined bit. As a result, the ALPG 4 reads and executes a test program according to the above specification from the ALPG memory 3, generates access timing and test pattern data according thereto, and accesses the DRAM memory array 2a. (Step ST1). Here, for example, it is assumed that the ALPG 4 repeats write and read accesses to one memory cell of a DRAM memory cell array a plurality of times.
    [56] Specifically, in the write access, the ALPG 4 generates an address signal for specifying the address of the memory cell to be data written in accordance with the write access timing described in the access pattern program, so that the column in the DRAM core 2. Send to the row decoder. The column row decoder decodes the address signal from the ALPG 4 and converts it into address information on the DRAM memory array. This address information is sent to a word driver and a bit line selection circuit to select a memory cell for data writing. For each memory cell selected in this way, the ALPG 4 writes test pattern data. On the other hand, in the read access, the target memory cell is selected as described above, and the ALPG 4 reads data.
    [57] At this time, if there is a defect in the DRAM memory cell, the defective data is written into the DRAM memory cell by access of the ALPG 4. In other words, the DRAM memory cell holds bad data even after the access is made by the ALPG 4. For example, when the charge of an arbitrary DRAM memory cell reaches the H level in the write access by the ALPG 4, the memory cell is defective, and the leakage current flows beyond the specified value, resulting in a potential drop. do.
    [58] Here, when the ALPG 4 sets the word line to the H level for data reading, the MOS transistor of the corresponding memory cell is brought into a conductive state. At this time, the potential held by the memory cell is further lowered by the parasitic capacitance of the bit line. In this state, when the charge of the bit line is read through the sense amplifier as the storage data of the memory cell, the determination value is reversed. That is, by the read access from the ALPG 4, the stored contents of the memory cell are read out as L level data.
    [59] Thereafter, even if normal data is written to the corresponding memory cell, the defective state is written again in the read access execution as described above. For this reason, the bad state is maintained even after the access is performed by the ALPG 4. Thus, even after the CPU 6 accesses the DRAM memory cell after completion of the access by the ALPG 4, the defective state of the memory cell can be read.
    [60] Upon completion of the series of accesses to the DRAM by the ALPG 4 described above, the CPU 6 interprets the test program set in the program memory area 7a to obtain a relationship between the DRAM memory cell and its response output expected value. The data written in the DRAM memory array 2a is read again using these address information. Here, data gradually read from each memory cell is temporarily stored in the buffer memory 12.
    [61] Subsequently, the CPU 6 gradually reads output data of the DRAM memory cells from the buffer memory 12 and performs a logical comparison with the response output expected value corresponding thereto. At this time, if the two do not match, the CPU 6 determines that the corresponding memory cell is defective, and gradually stores the defective information in the ES memory area 7b in the SRAM 7 (step ST2, failure determination step).
    [62] If a defect is found in the DRAM memory cell as described above, the CPU 6 executes a relief analysis program stored separately from the test program in the program memory area 7a, thereby executing the ES memory area 7b. Based on the stored contents, a set of replacement addresses (redundancy relief) for determining the row or column for efficiently saving the defective memory cell in the DRAM memory array 2a is obtained.
    [63] Based on the redundant redundancy solution obtained for the defective memory cell, the CPU 6 generates compressed information obtained by compressing the defective information in a relief unit. For example, if the DRAM memory array 2a has a configuration for performing redundancy relief in units of bit lines including defective memory cells, the defective information on a plurality of memory cells having different addresses on the same line is replaced with one data. By doing so, data is compressed. The compressed information thus obtained is stored in the ES memory area 7b in a series of operations in the read access.
    [64] Subsequently, the CPU 6 performs a test on all the memory cells (including the spare cells) of the DRAM memory array 2a under test, and gradually stores the defective information in the ES memory area 7b as compressed information. do.
    [65] When all the memory cells of the DRAM memory array 2a under test have been tested, the CPU 6 must interpret the compression information stored in the ES memory area 7b and laser trim in the LT-fuse 9. The rescue code (including the rescue code for the spare cell) specifying the part to be obtained is obtained (step ST3, rescue analysis step). The relief code is stored in the RC memory area 7c in the SRAM 7.
    [66] Thereafter, the relief code of the RC memory area 7c is read by an external test apparatus such as an LSI tester, and actual defective relief is performed.
    [67] As described above, since the DRAM is separated into two stages of access from the ALPG 4 and failure analysis by the CPU 6, and the DRAM is tested and repaired at high speed, the first memory for the ALPG ( 3) and only the data writing to the SRAM 7 and the reading of the last relief code become low speed processing by an external test apparatus such as an LSI tester. That is, even a low-cost, low-cost tester can perform high speed processing.
    [68] As described above, according to the first embodiment, a test-dedicated circuit is used by using the CPU 6 mounted as the logic circuit unit 5 and the SRAM 7 for execution code storage in the program processing thereof. Since failure determination and rescue analysis of the executed DRAM memory cells are performed by software processing by the CPU 6, the circuit scale can be reduced while maintaining the advantages such as real-time testing.
    [69] (Example 2)
    [70] FIG. 4 is a diagram showing a schematic configuration of a semiconductor integrated circuit device according to a second embodiment of the present invention, and FIG. 5 is a diagram showing a configuration for performing defect relief analysis of DRAM of the semiconductor integrated circuit device shown in FIG. 4. . In the figure, reference numeral 4a is an ALPG unit, and is composed of an ALPG 4 and a comparison circuit 14. Denoted at 13 is a failure determination flag in which the presence or absence of a failure in each block (hereinafter referred to as an analysis block) corresponding to any relief unit of the DRAM memory array 2a is set. Reference numeral 14 denotes a comparison circuit (comparison circuit section) constituting the ALPG section 4a, which compares the output data from the DRAM with an expected value and performs a defect determination. Reference numeral 15 denotes a selector which receives address information of a defective memory cell and obtains address information of an analysis block including the same. In addition, the same code | symbol is attached | subjected to the same component as FIG. 1 and FIG. 2, and the overlapping description is abbreviate | omitted.
    [71] Next, the operation will be described.
    [72] FIG. 6 is a flowchart showing the operation by the semiconductor integrated circuit device shown in FIG. 4, and the defect relief analysis operation of the DRAM will be described according to this drawing.
    [73] First, the recording circuit 8 inputs information necessary for a test such as a test program according to a test specification from an external test device such as an LSI tester. Thereafter, the write circuit 8 transmits the input test program to the program memory area 7a in the ALPG memory 3 and the SRAM 7 as execution codes (so-called machine code) of the ALPG 4 and the CPU 6. Set each one. This setting operation is performed in accordance with the data setting speed of the external test device.
    [74] Next, when the CPU 6 receives a test start request from the outside, the control register 11 stores a logic value specifying an access pattern program and a test vector of the test specification according to the request, and a logic value indicating the start of the test. ) Is set to a predetermined bit. As a result, the ALPG 4 reads and executes a test program according to the above specification from the ALPG memory 3, generates access timing and test pattern data according thereto, thereby accessing the DRAM memory array 2a. Run Here, for example, it is assumed that the ALPG 4 repeats write and read accesses to one memory cell of a DRAM memory cell array a plurality of times. The specific operation is the same as that of the first embodiment.
    [75] Subsequently, when a plurality of accesses to one memory cell are completed, the comparison circuit 14 detects the storage data of the memory cell specified by the address signal from the ALPG 4, and outputs the data from the memory cell. Enter as. Here, the comparison circuit 14 logically compares the expected value data input from the ALPG 4 and the corresponding output data. At this time, if the two do not match, the comparison circuit 14 determines that there is a failure for each analysis block, and sets the information indicating that there is a failure in the analysis block to which the corresponding memory cell belongs to the failure determination flag 13 (step). ST1a).
    [76] At the same time, address information of the defective memory cell is sent from the ALPG 4 to the selector 15. The selector 15 gradually inputs address information of the defective memory cell, obtains address information specifying the corresponding analysis block from address information of the defective memory cell included in the same analysis block, and stores it in the buffer memory 12.
    [77] When the series of accesses to the DRAM by the ALPG unit 4a described above is completed, the CPU 6 refers to the setting contents of the failure determination flag 13 and the address information of the analysis block stored in the buffer memory 12, The test program set in the program memory area 7a is analyzed and the relationship between each memory cell in the defective analysis block and its response output expected value is obtained. Thereafter, the CPU 6 performs data reading only for each memory cell in the analysis block by using the address information of each memory cell in the analysis block which has been defective. Here, the data gradually read out from each memory cell are temporarily stored in the buffer memory 12.
    [78] Subsequently, the CPU 6 gradually reads the output data of the memory cell from the buffer memory 12 and performs a logical comparison with the response output expected value corresponding thereto. At this time, if the two do not match, the CPU 6 determines that the corresponding memory cell is defective, and associates the defective information of the defective memory cell with the address information of the analysis block to the ES memory area 7b in the SRAM 7. Stored gradually (step ST2a, failure determination step).
    [79] Next, the CPU 6 executes a relief analysis program stored in the program memory area 7a separately from the test program, and based on the contents of the memory in the ES memory area 7b, the CPU 6 executes the analysis block. The compressed information obtained by compressing the defective information acquired on the basis of relief units is generated (step ST3a, failure determining step). For example, when a plurality of defective memory cells exist in a certain analysis block, data can be compressed by replacing these defective information with one data as the defective information about the corresponding analysis block. The compressed information thus obtained is stored in the ES memory area 7b in a series of operations in the read access.
    [80] Subsequently, the CPU 6 executes a test on all analysis blocks (including spare cells) that have been defective, and gradually stores the defective information in the ES memory area 7b as compressed information. Upon completion of the test of all the analysis blocks in which there was a defect, the CPU 6 interprets the compression information stored in the ES memory area 7b, and a remedy code that designates the portion of the LT-fuse 9 to be laser trimmed. (Including the rescue code for the spare cell) is obtained (step ST4a, rescue analysis step). The relief code is stored in the RC memory area 7c in the SRAM 7.
    [81] Thereafter, the relief code of the RC memory area 7c is read by an external test apparatus such as an LSI tester, and actual defective relief is performed.
    [82] As described above, according to the second embodiment, detailed defect determination and remedy analysis by the CPU 6 are performed only on the failure analysis block extracted by the failure determination of the DRAM by the ALPG unit 4a. The processing time for the missing analysis block can be reduced, and the test time can be shortened.
    [83] (Example 3)
    [84] FIG. 7 is a diagram showing a schematic configuration of a semiconductor integrated circuit device according to a third embodiment of the present invention, and FIG. 8 is a diagram showing a configuration for performing defect relief analysis of DRAM of the semiconductor integrated circuit device in FIG. . In the figure, reference numeral 16 denotes a rescue line flag in which information indicating whether or not a predetermined number or more of defective memory cells exist on a word line or a bit line in the DRAM memory array 2a is set. In addition, the same code | symbol is attached | subjected to the same component as FIG. 1 and FIG. 4, and the overlapping description is abbreviate | omitted.
    [85] Next, the operation will be described.
    [86] First, the recording circuit 8 inputs information necessary for a test such as a test program according to a test specification from an external test device such as an LSI tester. Thereafter, the write circuit 8 transmits the input test program to the program memory area 7a in the ALPG memory 3 and the SRAM 7 as execution codes (so-called machine code) of the ALPG 4 and the CPU 6. Set each one. This setting operation is performed in accordance with the data setting speed of the external test device.
    [87] Next, when the CPU 6 receives a test start request from the outside, the control register 11 stores a logic value specifying an access pattern program and a test vector of the test specification according to the request, and a logic value indicating the start of the test. Set to a predetermined bit of. As a result, the ALPG 4 reads and executes a test program according to the above specification from the ALPG memory 3, generates access timing and test pattern data according thereto, and accesses the DRAM memory array 2a. Run Here, for example, it is assumed that the ALPG 4 repeats write and read accesses to one memory cell of a DRAM memory cell array a plurality of times. The specific operation is the same as that of the first embodiment.
    [88] Subsequently, when a plurality of accesses to one memory cell are completed, the comparison circuit 14 detects the storage data of the memory cell specified by the address signal from the ALPG 4, and outputs the data from the memory cell. Enter as. Here, the comparison circuit 14 logically compares the expected value data input from the ALPG 4 and the corresponding output data. At this time, if the two do not match, the comparison circuit 14 determines that there is a failure for each analysis block, and sets the failure determination flag 13 to indicate that there is a failure in the analysis block to which the memory cell belongs.
    [89] At the same time, address information of the defective memory cell is sent from the ALPG 4 to the selector 15. The selector 15 gradually inputs address information of the defective memory cell, obtains address information specifying the corresponding analysis block from address information of the defective memory cell included in the same analysis block, and stores it in the buffer memory 12. The processing up to this point is the same as that of the second embodiment.
    [90] Further, defective information is gradually transferred to the CPU 6 from the ALPG 4 and the comparison circuit 14 via the buffer memory 12. Based on these defect information, the CPU 6 specifies a corresponding line in the rescue line flag 16 if, for example, two or more defective memory cells exist on a word line or a bit line in the DRAM memory array 2a. Set the information.
    [91] Subsequently, when a series of accesses to the DRAM by the ALPG unit 4a described above are completed, the CPU 6 executes a rescue analysis program stored in the program memory area 7a separately from the test program, and rescues. A rescue analysis for determining the replacement line of the line set in the line flag 16 is performed, and the result is stored in the ES memory area 7b.
    [92] Subsequently, the CPU 6 refers to the setting contents of the rescue line flag 16 and the failure determination flag 13 and the address information of the analysis block stored in the buffer memory 12, and the test set in the program memory area 7a. The program is analyzed to determine the relationship between each memory cell in the defective analysis block and its response output expected value. Thereafter, the CPU 6 reads data only for each memory cell in the analysis block. At this time, the memory cells on the line set in the rescue line flag 16 are not read out, and the following failure determination is not performed.
    [93] Next, the CPU 6 reads the output data of the memory cell gradually from the buffer memory 12 in the same manner as in the second embodiment, and performs a logical comparison with the response output expected value corresponding thereto. . At this time, if they do not match, the CPU 6 determines that the memory cell is defective, and associates the defective information of the defective memory cell with the address information of the analysis block to the ES memory area 7b in the SRAM 7. Store gradually (defect determination step).
    [94] Thereafter, the CPU 6 compresses the CPU 6 with respect to the defective information other than the line set in the rescue line flag 16 on the basis of the stored contents of the ES memory area 7b. The information is generated and stored in the ES memory area 7b.
    [95] Subsequently, the CPU 6 removes the thing related to the line set in the rescue line flag 16, performs a test on another analysis block (including the spare cell) that is defective, and uses the defective information as the compressed information. It is gradually stored in the memory area 7b. Upon completion of the test, the CPU 6 interprets the replacement line information or the compression information stored in the ES memory area 7b, and a rescue code (spare cell) that designates the portion of the LT-fuse 9 to be laser trimmed. (Including the remedy code for)). The relief code is stored in the RC memory area 7c in the SRAM 7.
    [96] Finally, the relief code of the RC memory area 7c is read by an external test apparatus such as an LSI tester, and actual defect relief is performed.
    [97] As described above, according to the third embodiment, a relief line flag 16 for specifying a line having a predetermined number or more of defective memory cells is provided, and a relief analysis is performed on the line without performing detailed defect determination. Because of this arrangement, the time required for rescue analysis can be reduced, and the test time can be shortened.
    [98] In addition, in Example 3, although the example which applied the relief line flag 16 to the structure which concerns on the said Example 2 was shown, it was applied to the structure which concerns on the said Example 1, and it was judged by the CPU 6, and a relief line flag was made. Even if the setting in (16) is executed, the same effect can be obtained.
    [99] As mentioned above, although the invention made by this inventor was demonstrated concretely according to the said Example, this invention is not limited to the said Example and can be variously changed in the range which does not deviate from the summary.
    [100] As described above, according to the present invention, when the test mode of the semiconductor memory device, which is composed of a plurality of memory cells and has a redundant configuration to replace defective parts, is set, the test data is written and stored in the memory cell in the semiconductor memory device. A redundancy structure in which the test access unit for reading and the data held in the memory cell at the time of data writing and reading by the test access unit are read again to determine the position of the defective portion in the semiconductor memory device and replace the defective portion. A central processing unit for interpreting the unit and a storage unit for storing the execution code, the failure determination result, and the analysis result of the operation in the test mode of the central processing unit are provided, so that the circuit scale can be reduced while maintaining the advantages such as real-time testing. It is said to have an effect.
    [101] According to the present invention, defects are set for each of the comparison circuit unit for comparing the data held in the memory cell with the expected value at the time of data writing and reading by the test access unit, and for each memory block corresponding to the replacement unit of the redundant configuration unit. And a failure determination flag, wherein the central processing unit again reads data only to the memory cells in the memory block in which the comparison result by the comparison circuit unit does not match and is set to be defective in the failure determination flag, thereby causing the memory block to be read again. Since the position determination of the defective part in the inside and the redundant component to replace the defective part are analyzed, the processing time for the memory block having no defect can be reduced, and the test time can be shortened.
    [102] According to the present invention, a semiconductor memory device is composed of bit lines and word lines arranged in a matrix shape, and a plurality of memory cells arranged on these lattice points, and is used for data writing and reading of the memory cells by the test access unit. And a relief line flag in which information specifying bit lines and / or word lines in which defective parts exist in a predetermined number or more is set, and the central processing unit must replace the bit lines and / or word lines set in the relief line flags. Since the analysis of the redundant redundant component is executed first, and the position of the defective part with respect to the bit line and / or word line is not determined, the time required for the relief analysis can be reduced, thereby reducing the test time. It is effective.
    权利要求:
    Claims (1)
    [1" claim-type="Currently amended] A semiconductor memory device comprising a plurality of memory cells and having a redundant configuration portion that replaces and repairs a defective portion;
    A test access unit which writes and reads test data to the memory cells in the semiconductor memory device when the operation mode is set to the test mode;
    A central processing unit that reads data held in a memory cell again during data writing and reading by the test access unit, and analyzes the position determination of the defective portion in the semiconductor memory device and the redundant configuration portion to replace the defective portion; ,
    A storage unit for storing the execution code of the operation in the test mode of the central processing unit, the failure determination result, and the analysis result
    Semiconductor integrated circuit device having a.
    类似技术:
    公开号 | 公开日 | 专利标题
    Huang et al.2003|Built-in redundancy analysis for memory yield improvement
    US8760949B2|2014-06-24|Mechanisms for built-in self repair of memory devices using failed bit maps and obvious repairs
    TWI220024B|2004-08-01|Hierarchical built-in self-test for system-on-chip design
    US6829181B1|2004-12-07|Semiconductor memory, method of testing semiconductor memory, and method of manufacturing semiconductor memory
    EP1377981B1|2007-06-06|Method and system to optimize test cost and disable defects for scan and bist memories
    EP1537586B1|2007-12-12|Circuit and method for testing embedded dram circuits through direct access mode
    US7155637B2|2006-12-26|Method and apparatus for testing embedded memory on devices with multiple processor cores
    US6681354B2|2004-01-20|Embedded field programmable gate array for performing built-in self test functions in a system on a chip and method of operation
    US8615688B2|2013-12-24|Method and system for iteratively testing and repairing an array of memory cells
    US6643807B1|2003-11-04|Array-built-in-self-test | for efficient, fast, bitmapping of large embedded arrays in manufacturing test
    JP3006303B2|2000-02-07|Array built-in self test | system
    US7260758B1|2007-08-21|Method and system for performing built-in self-test routines using an accumulator to store fault information
    US7484141B2|2009-01-27|Semiconductor device capable of performing test at actual operating frequency
    US6728910B1|2004-04-27|Memory testing for built-in self-repair system
    US7350119B1|2008-03-25|Compressed encoding for repair
    US6477672B1|2002-11-05|Memory testing apparatus
    US5659551A|1997-08-19|Programmable computer system element with built-in self test method and apparatus for repair during power-on
    US6233182B1|2001-05-15|Semiconductor integrated circuit and method for testing memory
    US7962809B1|2011-06-14|Method and apparatus for improving memory operation and yield
    US7561482B2|2009-07-14|Defective block isolation in a non-volatile memory system
    US7155643B2|2006-12-26|Semiconductor integrated circuit and test method thereof
    US7149921B1|2006-12-12|Apparatus, method, and system to allocate redundant components with subsets of the redundant components
    US7228468B2|2007-06-05|Method and apparatus of build-in self-diagnosis and repair in a memory with syndrome identification
    US8659961B2|2014-02-25|Memory repair systems and methods for a memory having redundant memory
    US6691252B2|2004-02-10|Cache test sequence for single-ported row repair CAM
    同族专利:
    公开号 | 公开日
    JP2003324155A|2003-11-14|
    US20030204783A1|2003-10-30|
    DE10254454A1|2003-11-20|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2002-04-30|Priority to JPJP-P-2002-00129071
    2002-04-30|Priority to JP2002129071A
    2003-01-13|Application filed by 미쓰비시덴키 가부시키가이샤
    2003-11-05|Publication of KR20030085466A
    优先权:
    申请号 | 申请日 | 专利标题
    JPJP-P-2002-00129071|2002-04-30|
    JP2002129071A|JP2003324155A|2002-04-30|2002-04-30|Semiconductor integrated circuit device and test method thereof|
    [返回顶部]